The present disclosure relates generally to integrated circuit (IC) designs, and more specifically to a layout design of six-transistor (6T) static random access memory (SRAM) cell.
A standard 6T SRAM cell has six transistors formed on a bulk semiconductor substrate. Among the six transistors, four are N-channel devices (NMOS transistors) categorized according to their functions as two pull-down transistors and two pass-gate transistors. The remaining two transistors are P-channel devices (PMOS transistors) functioning as pull-up transistors.
Conventionally, the pull-down transistor is located next to the pass-gate transistor, wherein an N-type doped region is implemented as the drains and the sources for both transistors. The pull-down transistors are required to withstand a high level of current, and are therefore designed to be large in physical size. Compared to the pull-down transistors, the pass-gate transistors are designed to be much smaller in physical size as they are not required to withstand such high level current. Thus, the doped regions of the pull-down transistors can be much wider than those of their adjacent pass-gate transistors. Due to the mismatched sizes of the pull-down transistor and the pass-gate transistor, the conventional SRAM cell is particularly susceptible to reliability defects caused by deviation of fabrication process.
Desirable in the art of IC designs are additional designs that can eliminate the width mismatch issue while reducing the overall size of the 6T SRAM cell.